Tamil Nadu government and iVP Semi launch ‘TN 100 Chip Varsity’ project to build semiconductor talent network

In a major step towards strengthening Tamil Nadu’s semiconductor ecosystem, Guidance Tamil Nadu, in partnership with iVP Semi has launched the ‘TN 100 Chip Varsity’ programme.

Under this programme, Guidance Tamil Nadu and iVP Semi will jointly support the creation of a Statewide network of chip design facilities embedded within engineering colleges. The project has a dual mandate: enabling the development of 100 new chip designs and training 5,000 students in advanced semiconductor design skills annually.

An MoU formalising this collaboration was signed recently at the TN Rising Coimbatore conclave, in the presence of Tamil Nadu Chief Minister M.K. Stalin. “We will help in establishing chip design labs across academic institutions in Tamil Nadu. We will give them certain products to design. And in the next five years, more than 1,000 products will come out of colleges and universities in the State,” P. Raja Manickam, CEO of iVP Semi, told The Hindu.

The programme will identify and onboard eligible colleges across Tamil Nadu, equipping them with industry-grade tools, curricula, and mentorship from global semiconductor experts. By exposing students to real-world chip development environments, the initiative aims to create a future-ready workforce and significantly expand Tamil Nadu’s semiconductor talent pool.

According to Mr. Manickam, a few colleges have already been zeroed in for this project. Some more have reached out, he said. SRM Institute of Science and Technology is one of the institutions and they have already been given chips for training. Through this initiative, iVP Semi aims to give 2-3 chips per college.

Tamil Nadu is betting big to grab a major share in the semiconductor pie. In August 2025, the Tamil Nadu government sanctioned the Semiconductor Design Promotion Scheme under its ₹500-crore Tamil Nadu Semiconductor Mission 2030 (TNSM 2030). The State is also making a strong push to set up Centres of Excellence (CoEs) to provide infrastructure required for chip design, testing, and validation.